1. Field of the Invention
The present invention generally relates to a memory circuit having a normal operation mode and a power-down mode, and particularly to a memory circuit for preventing the unnecessary rise of the power source potential supplied to the memory cell array during the power-down mode.
2. Description of the Related Art
A dynamic RAM generates a stable internal power source based on an external power source supplied externally, and drives the internal circuits with this internal power source. Further, in order to keep power consumption constant during the normal operation mode, the dynamic RAM generates a lower level power source for cell array which is stepped down from the external power source, and supplies this to the memory cell array occupying a large portion within the chip. This lower level cell array power source is specifically used as the power source of the sense amplifier for driving the bit line, and the voltage of the bit line amplified up to the cell array power source becomes the H level voltage accumulated in the memory cell.
FIG. 1 is an overall schematic diagram of a conventional dynamic RAM. The memory circuit depicted in FIG. 1 comprises a cell array 1 having a plurality of memory cells, a peripheral circuit 2 thereof, a cell array power source generation circuit 3 for generating a cell array power source V1 from an external power source Vcc, an internal power source generation circuit 4 for generating an internal power source Vii from an external power source, and a boosted power source generation circuit 5 for generating a boosted power source Vpp from an external power source Vcc. Circuits within the chip are basically driven with the internal power source Vii. Nevertheless, the cell array power source V1 for driving the sense amplifier and the boosted power source Vpp for driving the word line are additionally supplied to the cell array 1 as a special internal power source.
The cell array power source generation circuit 3 comprises at the final stage an N channel transistor N8, having a gate to which a constant voltage Vg1 is supplied, a drain connected to an external power source Vcc, and a source for outputting the cell array power source V1. This cell array power source V1 is supplied to the cell array 1, and supplies current to the sense amplifier circuit which operates in accordance with the reading, writing, and refreshing at the cell array. The transistor N8 is designed to be of a size sufficient for supplying such current.
Meanwhile, the dynamic RAM has a normal operation mode for conducting such operations of reading, writing and refreshing, and a power-down mode for conserving power consumption by stopping a large portion of the internal circuits at which the aforementioned operations are not conducted. In this power-down mode, the reading and writing operations during the normal operation mode are not conducted. Therefore, there is no driving of a sense amplifier accompanying these operations and hardly any current flows to the transistor N8 at the final stage of the cell array power source generation circuit 3. More precisely, although the self-refresh operation for activating the cell array is conducted in fixed intervals, as these intervals are of long cycles, the period in which the current hardly flows to the transistor N8 is sufficiently longer.
FIG. 2 is a diagram illustrating an example of the properties of the current and voltage of the cell array power source generation circuit. The horizontal axis is the source current I of the final stage transistor N8, and the vertical axis is the voltage of the cell array power source V1. As clear from this diagram regarding properties, when the current I is approximately 1 mA, for example, the cell array power source V1 is within the range of a desired voltage (1.5xc2x10.1 V). This voltage is of a level in which the approximate threshold value voltage of the transistor N8 is subtracted from the gate voltage Vg1. Nevertheless, when the source current I decreases, the cell array power source V1 rises as electric charge is accumulated in the load capacity relating to the cell array power source V1. In the example of FIG. 2, when the source current I decreases to approximately below 20 xcexcA, the cell array power source V1 becomes higher than a desired voltage range (1.5xc2x10.1 V for example).
As described above, the source voltage V1 rises when the source current I decreases, and, eventually, the transistor N8 operates in a so-called sub-threshold region as the voltage between the gate-source will become lower than the threshold voltage. Moreover, when the source current becomes 0, the source voltage V1 becomes substantially equivalent to the external power source Vcc.
Therefore, in the aforementioned power-down mode where the power consumption becomes extremely small in the cell array, the source current I decreases and the cell array power source V1 rises to a higher voltage than that during the normal operation mode (1.5xc2x10.1 V). Here, for example a large capacity (C1), including parasitic capacity, is disposed in order to prevent the noise of the cell array power source V1 or to stabilize the potential, accumulated will be a change of xcex94Vxc3x97C1, xcex94V is a difference of the potential from the desired voltage range. If this change is not consumed immediately after returning to the normal operation mode from the power-down mode, the cell array voltage V1 remains at a level higher than the normal level and the drive voltage V1 on the H level-side of the sense amplifier will become higher than normal. Thus, the bit line pre-charge level, which is the intermediate voltage between the H level (cell array power source V1) and the L level (ground) of the bit line, becomes higher than desired level. During the reading operation conducted by driving the word line at the following cycle, generating a minute voltage to the bit line pair and detecting the minute voltage with the sense amplifier, the voltage difference between the cell accumulated potential at the H level side having the normal cell array voltage and the aforementioned bit line pre-charge level which is higher than desired level becomes smaller than normal, and problems may arise in which such difference is judged as an erroneous data.
Accordingly, with the conventional example, voltage of the cell array power source V1 would differ during the normal operation mode, where the memory circuit is in an active state, and the power-down mode. This led to the possibility of malfunctions as described above.
Thus, an object of the present invention is to provide a memory circuit capable of preventing the occurrence of such malfunctions by keeping the voltage of an internal power source, such as a cell array power source, the same level during the normal operation mode and the power-down mode.
One aspect of the present invention for achieving the aforementioned object is that, in a memory circuit comprising a cell array and peripheral circuit, the cell array power source is supplied to a circuit which operates during the power-down mode in addition to the cell array. The circuit which operates during the power-down mode in a preferred embodiment is, for example, a self-refresh circuit. A dynamic memory requires refreshing operations in fixed intervals even during the power-down mode. Therefore, the self-refresh circuit is operating even during the power-down mode. Thus, by supplying the cell array power source to the self-refresh circuit, it is possible to consume a prescribed quantity of current from the cell array power source generation circuit to an extent of being able to maintain the level thereof even during the power-down mode. The cell array power source may be maintained within an appropriate voltage range thereby.
The self-refresh circuit includes an oscillation circuit which is constantly in operation, a frequency division circuit for dividing the output of the oscillation circuit, a timing signal generation circuit for generating a long-cycle self-refresh activation timing signal from such division circuit, and so on. By supplying the cell array power source to any one or a plurality of these circuits, or to a power source of apart of these circuits, it is possible to prevent the rise of the voltage level of the cell array power source.